Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new ®ve parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors Db/b, threshold voltages DVT0, bulk threshold parameters Dg, and two components for the mobility degradation parameter mismatch Dyo and Dye. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this ®ve parameter mismatch model, an extraordinary ®t between experimental and computed mismatch is obtained, including minimum length (1 mm) transistors for both ohmic and saturation regions. Standard deviations for these ®ve parameters are obtained as well as their respective correlation coef®cients, and are ®tted to two dimensional surfaces f…W, L† so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.